1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a shallow trench isolation (STI), structure featuring a group of silicon oxide and silicon nitride insulator liners on the sides of the shallow trench shape used to accommodate the STI structure.
2. Description of Prior Art
The ongoing quest for to form smaller semiconductor chips, still providing device densities equal or greater than device densities found with larger semiconductor chips, necessitated the use of new device isolation structures, structures that would consume less area than previously used isolation regions, formed via local oxidation of silicon (LOCOS), procedures. The presence of birds beak, or oxide encroachment into regions reserved for active device regions, encountered when applying LOCOS isolation procedures, resulted in the semiconductor industry shifting to STI structures, wherein the procedure for forming the STI structures does not consume adjacent active device area. The formation of STI structures however present a different set of process concerns that if not addressed can deleteriously influence device yield and performance. For example wet etch procedures encountered during routine device fabrication procedures can result in removal of a top portion of an insulator liner layer resulting in a gap or a divot located between the STI structure and the adjacent active device region. The unwanted divot can trap unwanted materials or create an area where conductive bridging can occur, in both cases adversely influencing device yield and parametrics. In addition when the active device region is comprised with a P well region, provided for accommodation of N channel, metal oxide semiconductor (NMOS), devices, segregation of the P type dopants in the well region, into undoped insulator liner layers or into an undoped insulator fill of the STI structure, can occur during high temperature process steps such as source/drain anneal procedures. The depletion of dopant in the P well region can result in unacceptable parametrics such as low threshold voltages, specifically for narrow width devices.
This invention will describe a process for fabricating a STI structure in which multiple composite insulator liner layers are used on the exposed surfaces, the sides and bottom of a shallow trench shape, to alleviate formation of the unwanted divot or gap in the insulator liner layer, located at the STI-active device region interface, in addition to preventing segregation of dopants from a active device region to components of the STI structure. Prior art such as Thei et al, in U.S. Pat. No. 6,350,662 B1, Jang et al, in U.S. Pat. No. 6,037,018, Huang et al, in U.S. Pat. No. 6,323,106 B1, and Akatsu et al, in U.S. Pat. No. 6,319,794 B1, describe methods of forming STI structures with various insulator, and composite insulator liner layers, located on the sides of shallow trench shapes. However none of these prior arts describe the formation of a group of insulator liner layers located on the exposed surfaces of the shallow trench shape, offering increased protection against unwanted divot formation, and against dopant depletion specifically occurring at the edge of the active device region located adjacent to the STI structure.
It is an object of this invention to form a shallow trench isolation (STI), structure for metal oxide semiconductor field effect (MOSFET), devices.
It is another object of this invention to form a shallow trench shape in a top portion of a semiconductor substrate, with the bottom of the shallow trench shape exhibiting rounded corners.
It is still another object of this invention to form a group of insulator liner layers, each comprised of either silicon nitride or silicon oxide, on the sides and bottom of a shallow trench shape.
In accordance with the present invention a method of forming an STI structure in a top portion of a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of a shallow trench shape, is described. A well region is formed in a top portion of a semiconductor substrate, followed by formation of a masking composite insulator layer comprised of an underlying pad silicon dioxide layer and an overlying silicon nitride layer. A shallow trench shape is defined in the composite insulator layer and in a top portion of the well region. Thermal growth of, followed by removal of, a silicon dioxide layer results in rounded corners at the bottom of the shallow trench shape. Atomic layer deposition procedures are used to deposit a group of insulator layers, comprised of a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer, on the surfaces of the shallow trench shape, as well as on the top surface of the masking composite insulator layer. After filling of the shallow trench shape with a high density plasma (HDP), deposited silicon oxide layer, chemical mechanical polishing (CMP), procedures are used to selectively remove the portions of HDP silicon oxide layer from the top surface of the masking composite insulator layer resulting in the STI structure, lined with the multiple insulator liner layers. A high temperature anneal is followed by removal of the portions of the group of insulator liner layers, and of the masking composite insulator layer, located on the top surface of the semiconductor surface, exposing the subsequent active device regions, located adjacent of the STI structure.